It has been practiced in recent years to fabricate a semiconductor device of high functionality as a plural number of semiconductor chips with different functions are housed in one and the same package. This sort of the semiconductor device, termed a multichip package (MCP), is disclosed in Patent Document 1, for example. The MCP is stirring up notice in view of its merits that the semiconductor device may be fabricated more easily and more inexpensively than an SoC (System-on-Chip) in which a plural number of functions are integrated in one and the same chip.
An example of the MCP is one in which a logic chip and a memory chip are packaged together. As for the logic chip, its operating voltage has been lowered appreciably because miniaturization is going on at a rapid pace for achieving high performance and low power consumption. On the other hand, there is an occasion where a memory chip of only a small capacity may be sufficient for use in the MCP. Thus, the fabrication technique several generations before may be used for fabricating the memory chip of the small capacity. However, the operating voltage for such small-capacity memory chip may be relatively high from time to time.
In such case, plural semiconductor chips differing in the operating voltage may need to be used in combination.
If, when the semiconductor chips, differing in the operating voltage, are used in combination, the semiconductor chip having a higher operating voltage directly outputs a data signal, the operating voltage of which is HIGH, to the semiconductor chip having a lower operating voltage, there is a possibility of destruction of transistors constituting an input circuit of the receiving semiconductor chip operating at the lower operating voltage.
On the other hand, if the semiconductor chip, operating at a lower voltage, directly transmits a data signal, having the low voltage as a HIGH level signal, to the semiconductor chip operating at a high voltage, there is a possibility that the logic of an input circuit of the semiconductor chip operating at the higher voltage cannot be determined as normally.
Heretofore, the above problems have been dealt with in the following manner.
That is, the conventional practice in combining a memory chip, operating at 1.5V, with a logic chip operating at 1.0V, has been to provide a 3.3V power supply unit in each of the memory chip and the logic chip, and also to provide an input/output circuit, operating at 3.3V, within each of the chips. In short, a buffer circuit for equating the input/output voltages between the chips is provided in each of the chips.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2005-217205A